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2.1 Chisel Module

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2.1 Chisel Module

Module

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// a class extends to built-in Chisel class 'Module'
class Passthrough extends Module {
  // io: must be called 'io' and be an 'IO' object or instance
  val io = IO(new Bundle {
    // Type: Uint, Width: 4
    val in = Input(UInt(4.W))
    val out = Output(UInt(4.W))
  })
  // ':=' is a Chisel operator (assign)
  io.out := io.in
}

Module Generator

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// parameterize
class PassthroughGenerator(width: Int) extends Module { 
  val io = IO(new Bundle {
    val in = Input(UInt(width.W))
    val out = Output(UInt(width.W))
  })
  io.out := io.in
}
// generate module with different widths
println(getVerilog(new PassthroughGenerator(10)))
println(getVerilog(new PassthroughGenerator(20)))

Tester

poke, expect, peek

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test(new Passthrough()) { c =>
    c.io.in.poke(0.U)     // Set our input to value 0
    c.io.out.expect(0.U)  // Assert that the output correctly has 0
    c.io.in.poke(1.U)     // Set our input to value 1
    c.io.out.expect(1.U)  // Assert that the output correctly has 1
}
println("SUCCESS!!")
println(c.io.out.peek())

Generate Verilog/ firrtl

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println(getVerilog(new Passthrough))
println(getFirrtl(new Passthrough))

println/ printf/ log

scala print

  • s 插值器

    在任何字符串前加上s，就可以直接在串中使用变量了。

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    val name="James"
    println(s"Hello,$name")
    println(s"1+1=${1+1}")
  • f 插值器

    在任何字符串字面前加上 f，就可以生成简单的格式化串。

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    val height=1.9d
    val name="James"
    println(f"$name%s is $height%2.2f meters tall")
    • raw 插值器

除了对字面值中的字符不做编码外，raw 插值器与 s 插值器在功能上是相同的。

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println(s"a\nb")	// a
        					// b
println(raw"a\nb")	// a\nb

chisel print

  • Chisel generator prints during circuit generation
  • Circuit prints during circuit simulation
  • Tester prints during testing
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class PrintingModule extends Module {
    val io = IO(new Bundle {
        val in = Input(UInt(4.W))
        val out = Output(UInt(4.W))
    })
    io.out := io.in

    // chisel p interpolator
    // only when simulation, print every setp(1)
    printf(p"Print during simulation: IO is $io\n")
    
	// only when simulation, print every setp(1)
    printf("Print during simulation: Input is %d\n", io.in)
    
    // only when generation
    // println is a built-in Scala function that prints to the console. 
    // It cannot be used to print during circuit simulation, 
    // because the generated circuit is FIRRTL or Verilog- not Scala.
    println(s"Print during generation: Input is ${io.in}")
}

test(new PrintingModule ) { c =>
    c.io.in.poke(3.U)
    c.clock.step(2) // circuit will print
    
    // only when testing
    println(s"Print during testing: Input is ${c.io.in.peek()}")
}
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Elaborating design...
Print during generation: Input is UInt<4>(IO in unelaborated PrintingModule)
Done elaborating.
Print during simulation: Input is   3
Print during simulation: IO is AnonymousBundle(in ->   3, out ->   3)
Print during simulation: Input is   3
Print during simulation: IO is AnonymousBundle(in ->   3, out ->   3)
Print during testing: Input is UInt<4>(3)
Print during simulation: Input is   0
Print during simulation: IO is AnonymousBundle(in ->   0, out ->   0)
test PrintingModule Success: 0 tests passed in 4 cycles in 0.020066 seconds 199.34 Hz